Address translation

General purpose CPUs often utilize virtual memory, allowing programs to operate in their own distinct address space or in a shared virtual address space. This virtual addressing system simplifies program design, as it interacts with the virtual addresses rather than the direct physical addresses. The translation from virtual to physical addresses is managed by the memory management unit (MMU) with the assistance of the translation lookaside buffer (TLB), a cache of mappings; crucial aspects of this translation include latency in address availability, the potential for multiple virtual addresses to correspond to a single physical address, and the division of the virtual address space into pages of varying sizes.