Verifications and Uses

Formal verification

Formal verification is the process of using mathematical methods to prove or disprove the correctness of algorithms in hardware and software systems. It can be used to verify systems such as cryptographic protocols, circuits, and software code by providing a formal proof on an abstract mathematical model of the system. Mathematical objects like finite-state machines and Petri nets are often used to model these systems.

1 courses cover this concept

15-317 / 15-657 Constructive Logic

Carnegie Mellon University

Fall 2021

This undergraduate course introduces students to constructive logics such as intuitionistic and linear logic, focusing on their use in computer science. The goal is to understand the distinction between classical and constructive logic, define logical connectives, implement theorem provers, and explore computational interpretations of logics. Concepts covered include natural deduction, sequent calculus, logic programming, linear logic, and many more.

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